The present invention relates to a matrix liquid crystal display device, more particularly, to the drive circuit of a matrix liquid crystal display device provided with switching transistors connected to each picture element of the matrix display pattern.
Conventionally, it is well known that, even when a small-duty drive or multi-line multiplex drive is performed, a high-contrast display equivalent to a static-drive display can be achieved in such a matrix liquid crystal display device using switching transistors built in the LCD panel. Typically, such a liquid crystal display device has a circuit configuration and signal waveforms shown in FIG. 1. In FIG. 1, reference number 11 indicates the LCD panel, and a switching transistor 11-c is connected to the crossing of row electrode 11-a and column electrode 11-b. Reference number 12 indicates a row electrode driver mainly composed of a shift register, which outputs scan pulse S to each row electrode by sequentially shifting this pulse by using clock pulse .phi.1 delivered from the signal controller 13. Reference 14 indicates a column electrode driver mainly composed of a shift register and a sample holder, which samples data sent in series from a data controller 15 with such a timing that corresponds with each column electrode synchronous with clock pulse .phi.2, and then holds a sample value for one scan period (F) before eventually sending it to respective column electrodes.
Of a plurality of the data signal voltages dealing with respective picture elements and arriving in series, the column electrode driver 14 in the drive circuit actually samples only such a voltage which is exactly in the period dealing with picture elements of the corresponding column, and then simultaneously delivers the sampled voltage to all of the column electrodes during the next one-scan period. A typical example of this drive circuit is shown in FIG. 2. Reference numbers 21 and 22 respectively indicate electric switches which turn ON themselves when control signals Pa and Pb are received. When the electric switch 21 momentarily turns ON upon receipt of the control signal Pa dealing with the corresponding column, the data voltage at this moment is charged into capacitor 23. After completing samplings from all columns, the control signal Pb turns switch 22 ON immediately before the sampling from the first column is resumed, causing capacitor 23 to discharge its stored voltage to capacitor 24, and then this voltage is held during the next scan period. While this voltage still remains in capacitor 24, the next data voltage is sampled by capacitor 23. The sampled voltage held by capacitor 24 is then delivered as a load to the column electrode 26 via the output buffer circuit. It may be determined that the load corresponds to a capacitor that synthesizes both the liquid crystal capacitance and free capacitance of the switching transistors.
In this drive circuit, resistor 27 connected in series to load 26 discharges the charge stored in load 26. Transistor 25 of the output buffer is prepared to allow current to constantly flow in one direction, and therefore, if resistor 27 is absent, load 26 always charges itself without following any variation of input signals that require discharge. As a result, time constants CL and RL should be set at such values significantly less than the one-scan period. However, since current constantly flows through resistor 27, if there are many drive lines and large load, current consumption becomes a problem. Likewise, capacitance C1 should be set in this drive circuit at a value significantly greater than C2 to properly deliver the sampled voltage from capacitor 23 to capacitor 24. The reason for this is described below. If capacitances C1 and C2 were set at values close to each other, as shown by the equation Vg=(C1Vi+C2Vg')/(C1+C2) (where Vg' indicates the voltage charged in C2), the voltage Vg to be delivered from capacitor 23 to capacitor 24 can be varied by the voltage Vg' in capacitor 24 before the capacitance values of C1 and C2 and their voltages are delivered to capacitor 24, and as a result, the display of a certain row may be adversely affected by the display content of the preceding rows, making it difficult to delicately display interim tones. Nevertheless, from the viewpoint of current consumption and the needs for high-density part integration, it is not desirable to excessively expand the capacitance, since it will easily cause the display quality to degrade itself.